module z80_reg #(
    parameter REG_ADDR = 24'h000000
)(
    input  wire             clk,
    input  wire             resetn,
    input  wire      [1:0]  mem_ahb_htrans,
    input  wire             mem_ahb_hready,
    input  wire             mem_ahb_hwrite,
    input  wire      [31:0] mem_ahb_haddr,
    input  wire      [2:0]  mem_ahb_hsize,
    input  wire      [2:0]  mem_ahb_hburst,
    input  wire      [31:0] mem_ahb_hwdata,
    output wire             hreadyout,
    output wire      [31:0] hrdata
);

reg hreadyout_reg;
reg hreadyout_del;

// mcu write register
// *((int*)0x60000000) = value;
reg [31:0] hwdata_reg;
always @(posedge clk or negedge resetn) begin
	if (!resetn) begin
		hreadyout_reg <= 1'b1;
	end else if(mem_ahb_htrans == 2'b10 && hreadyout_reg) begin
		hreadyout_reg <= 1'b0;
	end else if(!hreadyout_del &&
		mem_ahb_hwrite &&
		mem_ahb_haddr[23:0] == REG_ADDR) begin
		hwdata_reg <= mem_ahb_hwdata;
		hreadyout_reg <= 1'b1;
	end else begin
		hreadyout_reg <= 1'b1;
	end
end

always @ (posedge clk or negedge resetn) begin
	if (!resetn) begin
 		hreadyout_del <= 1'b1;
	end else begin
		hreadyout_del <= hreadyout_reg;
	end
end

assign hreadyout = hreadyout_reg;

// mcu read
// int value = *((int*)0x60000000);
reg [31:0] hrdata_reg;
always @(posedge clk or negedge resetn) begin
	if (!resetn) begin
	end else if (mem_ahb_htrans == 2'b10 &&
		mem_ahb_hready &&
		!mem_ahb_hwrite &&
		mem_ahb_haddr[23:0] == REG_ADDR)
	begin
		hrdata_reg <= hwdata_reg;
	end
end

assign hrdata = hrdata_reg;

endmodule